EPC16QC100N vs EPC16SI16N Comparaison
Comparaison détaillée côte à côte de EPC16QC100N par Altera et EPC16SI16N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPC16QC100N | EPC16SI16N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $24,10 | $4,35 |
| Taille de mémoire | 16 Mbit (16,777,216 bits) | 16 Mb (16,777,216 bits) |
| Programmable Type | In System Programmable | — |
| Configuration Clock Frequency | 33 MHz max | — |
| On-Chip Decompression | Yes (supports compressed bitstreams) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Access Time | 90 ns typical | — |
| Flash Read Bandwidth | 160 Mbps (16-bit DQ at 10 MHz) | — |
| Configuration Interface | FPP / PS / AS via dedicated FPGA pins | — |
| JTAG (IEEE 1149.1) ISP | Supported | — |
| Température de fonctionnement | 0 C to 70 C | -40 C to +85 C (industrial, 'SI' suffix) |
| Boîtier | 100-pin PQFP (20 x 14 mm) | 16-pin SOIC (300 mil, 'SI' suffix) |
| Type de montage | Surface Mount | Surface Mount |
| Lead Free | Yes (per datasheet) | — |
| Packaging | Tray | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Type de mémoire | — | Non-volatile flash (enhanced configuration device) |
| Interface | — | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) |
| Programming Interface | — | JTAG (IEEE 1149.1 boundary scan) |
| Maximum Operating Frequency | — | 40 MHz (fast configuration mode) |
| Tension d'alimentation de fonctionnement | — | 3.3 V (typ) |
| Lead-Free / Finish | — | Lead-free (matte tin), 'N' suffix |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| Statut RoHS | — | Compliant |
| In-System Programmability | — | Yes (via JTAG, multiple reprogramming cycles) |
| Compatible FPGA Series | — | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III |
| Configuration Daisy-Chaining | — | Supported (multiple devices / multiple FPGAs) |
| On-Chip Charge Pump | — | Integrated (no external VPP required) |