EPC16QC100SS vs EPC16QC100DM Vergleich
Detaillierter Direktvergleich von EPC16QC100SS von Intel und EPC16QC100DM von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC16QC100SS - 16Mb Config PROM for FPGAs, PQFP-100 | Intel
EPC16QC100SS ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC16QC100SS | EPC16QC100DM |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $13,20 | $15,85 |
| Speichertyp | In-System Programmable Configuration PROM | Non-volatile Configuration PROM (NOR flash) |
| Speichergröße | 16 Mb (16,777,216 bits) | — |
| Configuration Interface | Passive Serial / Passive Parallel Synchronous / Passive Parallel Asynchronous | Serial (SPI-compatible, Altera FPP mode) |
| Operating Modes | FPGA configuration storage, ISP via IEEE 1532 | — |
| Supply Voltage (VCC) | 3.3 V (SS suffix variant) | — |
| I/O Logic Level | 3.3V or 2.5V selectable via VCCSEL | — |
| Betriebstemperatur | 0C to +70C (Commercial) | — |
| Gehäuse | 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm | 100-pin PQFP (QFPA) |
| Montageart | Surface Mount | — |
| Compatible FPGAs | Stratix, Stratix II, Cyclone, Cyclone II, APEX 20K, other Altera FPGAs requiring >8 Mbit configuration | — |
| Programmability | In-system programmable (IEEE 1532) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | Intel (formerly Altera) | — |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Core Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| I/O Voltage (VIO) | — | 2.5 V / 3.3 V selectable |
| Output Voltage (VPP) | — | 1.8 V / 2.5 V / 3.3 V selectable |
| Maximum DCLK Frequency | — | 40 MHz |
| Cascadable | — | Yes (multi-device daisy chain via nCASC) |
| In-System Programming | — | Yes (IEEE 1532 / JTAG) |
| Program/Erase Cycles | — | [DATA_NEEDED: program/erase cycle endurance] |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Betriebstemperaturbereich | — | -40 C to +85 C (industrial) |
| Package Code | — | Q100 + DM suffix |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | — | Stratix, Cyclone, APEX, ACEX |