EPC16QC100SS vs EPC16QC100DM Comparaison
Comparaison détaillée côte à côte de EPC16QC100SS par Intel et EPC16QC100DM par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC16QC100SS | EPC16QC100DM |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $13,20 | $15,85 |
| Type de mémoire | In-System Programmable Configuration PROM | Non-volatile Configuration PROM (NOR flash) |
| Taille de mémoire | 16 Mb (16,777,216 bits) | — |
| Configuration Interface | Passive Serial / Passive Parallel Synchronous / Passive Parallel Asynchronous | Serial (SPI-compatible, Altera FPP mode) |
| Operating Modes | FPGA configuration storage, ISP via IEEE 1532 | — |
| Supply Voltage (VCC) | 3.3 V (SS suffix variant) | — |
| I/O Logic Level | 3.3V or 2.5V selectable via VCCSEL | — |
| Température de fonctionnement | 0C to +70C (Commercial) | — |
| Boîtier | 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm | 100-pin PQFP (QFPA) |
| Type de montage | Surface Mount | — |
| Compatible FPGAs | Stratix, Stratix II, Cyclone, Cyclone II, APEX 20K, other Altera FPGAs requiring >8 Mbit configuration | — |
| Programmability | In-system programmable (IEEE 1532) | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | Intel (formerly Altera) | — |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Core Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| I/O Voltage (VIO) | — | 2.5 V / 3.3 V selectable |
| Output Voltage (VPP) | — | 1.8 V / 2.5 V / 3.3 V selectable |
| Maximum DCLK Frequency | — | 40 MHz |
| Cascadable | — | Yes (multi-device daisy chain via nCASC) |
| In-System Programming | — | Yes (IEEE 1532 / JTAG) |
| Program/Erase Cycles | — | [DATA_NEEDED: program/erase cycle endurance] |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Plage de température de fonctionnement | — | -40 C to +85 C (industrial) |
| Package Code | — | Q100 + DM suffix |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | — | Stratix, Cyclone, APEX, ACEX |