EPC16SI16N vs EPC16UI8B Vergleich
Detaillierter Direktvergleich von EPC16SI16N von Intel und EPC16UI8B von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPC16SI16N | EPC16UI8B |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,35 | $12,50 |
| Speichertyp | Non-volatile flash (enhanced configuration device) | — |
| Speichergröße | 16 Mb (16,777,216 bits) | — |
| Schnittstelle | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) | Active Serial (AS), JTAG |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Maximum Operating Frequency | 40 MHz (fast configuration mode) | — |
| Betriebsversorgungsspannung | 3.3 V (typ) | — |
| Betriebstemperatur | -40 C to +85 C (industrial, 'SI' suffix) | -40 C to +85 C (Industrial) |
| Gehäuse | 16-pin SOIC (300 mil, 'SI' suffix) | USON-8 / WSON-8 (8-pin) |
| Montageart | Surface Mount | Surface Mount |
| Lead-Free / Finish | Lead-free (matte tin), 'N' suffix | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| In-System Programmability | Yes (via JTAG, multiple reprogramming cycles) | — |
| Compatible FPGA Series | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III | — |
| Configuration Daisy-Chaining | Supported (multiple devices / multiple FPGAs) | — |
| On-Chip Charge Pump | Integrated (no external VPP required) | — |
| Memory Density | — | 16 Mbit (2 MB) |
| Funktion | — | Enhanced Configuration Device for SRAM-based LUT FPGAs |
| Versorgungsspannung | — | 2.5 V / 3.3 V |
| Architecture | — | Multi-page flash, up to 8 pages |
| In-System Programming | — | Yes (JTAG) |
| Compression Support | — | Yes (bitstream decompression) |
| Remote System Upgrade | — | Yes |
| Cascade Support | — | Yes (multi-FPGA) |
| Silicon Revision | — | B (second revision) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |