EPC1LC20-WCEC52 vs EPC1L20 Vergleich
Detaillierter Direktvergleich von EPC1LC20-WCEC52 von Altera und EPC1L20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC1LC20-WCEC52 | EPC1L20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,45 | $3,75 |
| Speichertyp | OTP Configuration PROM (Anti-fuse) | OTP Configuration PROM (Flash) |
| Speichergröße | 1 Mbit (1,048,576 bits) | 1 Mbit |
| Speicherorganisation | 212,942 x 1 bit | — |
| Schnittstelle | Serial (Altera FPP/PS configuration protocol) | Serial / FPP configuration + JTAG (IEEE 1149.1) |
| Configuration Clock (DCLK) | 8 MHz maximum | — |
| Supply Voltage (VCC) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V (FPGA interface) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Programmability | One-Time Programmable (OTP) | One-Time Programmable (OTP) |
| Betriebstemperatur | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Gehäuse | 20-pin PLCC (J-lead, through-hole, 9x9 mm) | 20-pin PLCC (9x9 mm) |
| Package Mounting | Through-hole (also accepts PLCC socket) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, MAX series | — |
| Programming Interface | JTAG (IEEE Std 1149.1) ISP | — |
| Pin-Anzahl | 20 | — |
| Lebenszyklusstatus | Obsolete (recommended replacement: EPCQ family or newer serial config devices) | — |
| Configuration Clock (max) | — | 8 MHz |
| Flash Access Time | — | 90 ns (approx.) |
| Max Read Bandwidth | — | 160 Mbps (16-bit DQ bus) |
| Versorgungsspannung | — | 3.3 V (typical) |
| Montageart | — | Through-Hole / Socket |
| JTAG / ISP Support | — | Yes (IEEE 1149.1) |
| Compatible FPGA Series | — | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families |