EPC1LC20-WCEC52 vs EPC1L20 Comparison

Detailed side-by-side comparison of EPC1LC20-WCEC52 by Altera and EPC1L20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC1LC20-WCEC52 EPC1L20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $7.45 $3.75
Memory Type OTP Configuration PROM (Anti-fuse) OTP Configuration PROM (Flash)
Memory Size 1 Mbit (1,048,576 bits) 1 Mbit
Organization 212,942 x 1 bit β€”
Interface Serial (Altera FPP/PS configuration protocol) Serial / FPP configuration + JTAG (IEEE 1149.1)
Configuration Clock (DCLK) 8 MHz maximum β€”
Supply Voltage (VCC) 3.3 V β€”
I/O Voltage Tolerance 5.0 V (FPGA interface) β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) β€”
Programmability One-Time Programmable (OTP) One-Time Programmable (OTP)
Operating Temperature -40C to +85C (industrial) [DATA_NEEDED: operating temperature range]
Package 20-pin PLCC (J-lead, through-hole, 9x9 mm) 20-pin PLCC (9x9 mm)
Package Mounting Through-hole (also accepts PLCC socket) β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free status]
Compatible FPGA Families Cyclone, Stratix, APEX, ACEX, MAX series β€”
Programming Interface JTAG (IEEE Std 1149.1) ISP β€”
Pin Count 20 β€”
Lifecycle Status Obsolete (recommended replacement: EPCQ family or newer serial config devices) β€”
Configuration Clock (max) β€” 8 MHz
Flash Access Time β€” 90 ns (approx.)
Max Read Bandwidth β€” 160 Mbps (16-bit DQ bus)
Supply Voltage β€” 3.3 V (typical)
Mounting Type β€” Through-Hole / Socket
JTAG / ISP Support β€” Yes (IEEE 1149.1)
Compatible FPGA Series β€” Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families

Datasheets & Resources

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