EPC2-TI32N vs EPC2-TC32 Vergleich
Detaillierter Direktvergleich von EPC2-TI32N von Intel und EPC2-TC32 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC2-TC32 - 1.6Mb ISP Configuration PROM | Altera | TQFP-32
EPC2-TC32 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC2-TI32N | EPC2-TC32 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $11,50 | $15,90 |
| Speichergröße | 1.6 Mb | 1.6 Mbit |
| Memory Organization | 1,695,680 x 1 | — |
| Programmable Type | In System Programmable | — |
| Schnittstellentyp | Serial (for SRAM-based LUT FPGAs) | Serial |
| Programming Interface | IEEE 1532-compliant JTAG | — |
| Supply Voltage - VCCINT | 3.0 V to 3.6 V | — |
| Supply Voltage - VCCIO | 4.5 V to 5.5 V | — |
| Betriebstemperatur | -40 C to +85 C | — |
| Gehäuse / Bauform | 32-TQFP (7 mm x 7 mm) | — |
| Montageart | Surface Mount | Surface Mount |
| Terminal Pitch | 0.8 mm | — |
| Supplier Device Package | 32-TQFP | — |
| Packaging | Tray | — |
| Technology | Flash + CMOS configuration logic | — |
| Configuration Clock | Dedicated DCLK output for FPGA | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Speichertyp | — | EPROM (OTP/UV-erasable configuration PROM) |
| Speicherorganisation | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Versorgungsspannung | — | 3.3 V |
| Betriebstemperaturbereich | — | 0C to +70C (Commercial) |
| Gehäuse | — | 32-pin TQFP (7x7 mm) |
| Supported FPGA Families | — | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Configuration Mode | — | Serial (FPP/MSD via FPGA master/slave) |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| MSL-Level | — | MSL 3 (168 hours) |