EPC2L20 vs EPC2LS20U Vergleich
Detaillierter Direktvergleich von EPC2L20 von Altera und EPC2LS20U von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2L20 | EPC2LS20U |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $25,80 | $4,25 |
| Speichertyp | Configuration PROM (non-volatile) | — |
| Speichergröße | 1.6 Mbit | — |
| Speicherorganisation | 8-bit byte | — |
| Schnittstelle | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) | Altera serial configuration / JTAG |
| Programmability | In-system programmable via JTAG | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (VCCSEL selectable) | — |
| Cascade Support | Yes - multi-device daisy chain | — |
| Boundary Scan | JTAG IEEE 1149.1 BST | — |
| Gehäuse | 20-pin PLCC (J-lead) | 20-PLCC (J-lead, 9x9 mm) |
| Montageart | Surface Mount (PLCC socket compatible) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: Operating Temperature] |
| MSL-Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL Level] |
| RoHS-Status | RoHS Compliant (per IC Components listing) | — |
| Process Technology | Low-power CMOS | — |
| Target FPGAs | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix | — |
| Product Type | — | In-System Programmable Configuration PROM |
| Memory Density | — | 1.6 Mbit |
| Operating Voltage (VCC) | — | 3.3 V |
| Programming Method | — | In-System Programmable (ISP) via JTAG |
| Lead-Free / RoHS | — | Yes (per "U" suffix) |
| Supported FPGA Families | — | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 |
| Configuration Modes | — | PS (Passive Serial), AS, FPP |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Done Pin | — | Yes (open-drain programmable polarity) |
| nSTATUS Pin | — | Yes (open-drain error flag) |
| nCONFIG Pin | — | Yes (reset/reconfiguration input) |
| DCLK Output | — | Yes (configuration clock to FPGA) |
| Compliance | — | RoHS (Pb-free per U suffix) |