EPC2L20 vs EPC2LS20U Comparación
Comparación detallada lado a lado de EPC2L20 por Altera y EPC2LS20U por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2L20 | EPC2LS20U |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $25,80 | $4,25 |
| Tipo de memoria | Configuration PROM (non-volatile) | — |
| Tamaño de memoria | 1.6 Mbit | — |
| Organización de memoria | 8-bit byte | — |
| Interfaz | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) | Altera serial configuration / JTAG |
| Programmability | In-system programmable via JTAG | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (VCCSEL selectable) | — |
| Cascade Support | Yes - multi-device daisy chain | — |
| Boundary Scan | JTAG IEEE 1149.1 BST | — |
| Encapsulado | 20-pin PLCC (J-lead) | 20-PLCC (J-lead, 9x9 mm) |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: Operating Temperature] |
| Nivel MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL Level] |
| Estado RoHS | RoHS Compliant (per IC Components listing) | — |
| Process Technology | Low-power CMOS | — |
| Target FPGAs | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix | — |
| Product Type | — | In-System Programmable Configuration PROM |
| Memory Density | — | 1.6 Mbit |
| Operating Voltage (VCC) | — | 3.3 V |
| Programming Method | — | In-System Programmable (ISP) via JTAG |
| Lead-Free / RoHS | — | Yes (per "U" suffix) |
| Supported FPGA Families | — | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 |
| Configuration Modes | — | PS (Passive Serial), AS, FPP |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Done Pin | — | Yes (open-drain programmable polarity) |
| nSTATUS Pin | — | Yes (open-drain error flag) |
| nCONFIG Pin | — | Yes (reset/reconfiguration input) |
| DCLK Output | — | Yes (configuration clock to FPGA) |
| Compliance | — | RoHS (Pb-free per U suffix) |