EPC2L20 vs EPC2LS20U Comparaison
Comparaison détaillée côte à côte de EPC2L20 par Altera et EPC2LS20U par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2L20 | EPC2LS20U |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $25,80 | $4,25 |
| Type de mémoire | Configuration PROM (non-volatile) | — |
| Taille de mémoire | 1.6 Mbit | — |
| Organisation de la mémoire | 8-bit byte | — |
| Interface | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) | Altera serial configuration / JTAG |
| Programmability | In-system programmable via JTAG | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (VCCSEL selectable) | — |
| Cascade Support | Yes - multi-device daisy chain | — |
| Boundary Scan | JTAG IEEE 1149.1 BST | — |
| Boîtier | 20-pin PLCC (J-lead) | 20-PLCC (J-lead, 9x9 mm) |
| Type de montage | Surface Mount (PLCC socket compatible) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: Operating Temperature] |
| Niveau MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL Level] |
| Statut RoHS | RoHS Compliant (per IC Components listing) | — |
| Process Technology | Low-power CMOS | — |
| Target FPGAs | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix | — |
| Product Type | — | In-System Programmable Configuration PROM |
| Memory Density | — | 1.6 Mbit |
| Operating Voltage (VCC) | — | 3.3 V |
| Programming Method | — | In-System Programmable (ISP) via JTAG |
| Lead-Free / RoHS | — | Yes (per "U" suffix) |
| Supported FPGA Families | — | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 |
| Configuration Modes | — | PS (Passive Serial), AS, FPP |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Done Pin | — | Yes (open-drain programmable polarity) |
| nSTATUS Pin | — | Yes (open-drain error flag) |
| nCONFIG Pin | — | Yes (reset/reconfiguration input) |
| DCLK Output | — | Yes (configuration clock to FPGA) |
| Compliance | — | RoHS (Pb-free per U suffix) |