EPC2L20N vs EPC2LC02N Vergleich
Detaillierter Direktvergleich von EPC2L20N von Altera und EPC2LC02N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2L20N | EPC2LC02N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,20 | $3,40 |
| Funktion | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs | — |
| Speichergröße | 1.6 Mbit | — |
| Programmable Type | In System Programmable (ISP) | — |
| Supply Voltage - VCCINT/VCCIO | 3.0 V to 3.6 V or 4.5 V to 5.5 V | — |
| Gehäuse / Bauform | 20-LCC (J-Lead), PLCC-20 | — |
| Packaging | Tube | — |
| Betriebstemperatur | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Supported FPGA Families | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) | APEX II, APEX 20K, ACEX 1K, FLEX 10K, Mercury, Stratix (partial) |
| Configuration Interface | Serial (Altera FPP / PS configuration scheme) | — |
| Cascade Support | Yes (multi-PROM chain via CE control) | — |
| Programming Method | In-system via 4-wire ISP / JTAG-style | — |
| Montageart | Surface Mount (J-Lead PLCC) | Surface Mount / Socket |
| Pin-Anzahl | 20 | — |
| Lead Finish | Matte Tin (Pb-free) | — |
| MSL-Level | 3 (168 hours) | [DATA_NEEDED: MSL level] |
| RoHS-Status | Compliant | — |
| Device Type | — | Enhanced Configuration Device (Configuration PROM) |
| Memory Density | — | 1.6 Mbit |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Schnittstelle | — | Serial or Parallel FPGA configuration, JTAG (IEEE 1149.1) ISP |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| Configuration Mode | — | Serial / Parallel / Multi-device daisy-chain |
| Gehäuse | — | 20-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Code | — | L (PLCC-20, leaded) |
| JTAG Compliance | — | IEEE 1149.1 (TAP controller with 4-wire interface) |
| DC Input Voltage (absolute max) | — | -0.3 V to +7.0 V (transients to -2.0 V / +7.0 V for <20 ns) |
| Lead-Free / RoHS | — | Lead finish version dependent (Pb-free and SnPb variants exist) |
| Programming Cycles | — | 100 typical (flash endurance, per datasheet) |