EPC2L20N vs EPC2LC02N Comparaison
Comparaison détaillée côte à côte de EPC2L20N par Altera et EPC2LC02N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2L20N | EPC2LC02N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,20 | $3,40 |
| Fonction | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs | — |
| Taille de mémoire | 1.6 Mbit | — |
| Programmable Type | In System Programmable (ISP) | — |
| Supply Voltage - VCCINT/VCCIO | 3.0 V to 3.6 V or 4.5 V to 5.5 V | — |
| Boîtier / Format | 20-LCC (J-Lead), PLCC-20 | — |
| Packaging | Tube | — |
| Température de fonctionnement | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Supported FPGA Families | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) | APEX II, APEX 20K, ACEX 1K, FLEX 10K, Mercury, Stratix (partial) |
| Configuration Interface | Serial (Altera FPP / PS configuration scheme) | — |
| Cascade Support | Yes (multi-PROM chain via CE control) | — |
| Programming Method | In-system via 4-wire ISP / JTAG-style | — |
| Type de montage | Surface Mount (J-Lead PLCC) | Surface Mount / Socket |
| Nombre de broches | 20 | — |
| Lead Finish | Matte Tin (Pb-free) | — |
| Niveau MSL | 3 (168 hours) | [DATA_NEEDED: MSL level] |
| Statut RoHS | Compliant | — |
| Device Type | — | Enhanced Configuration Device (Configuration PROM) |
| Memory Density | — | 1.6 Mbit |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Interface | — | Serial or Parallel FPGA configuration, JTAG (IEEE 1149.1) ISP |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| Configuration Mode | — | Serial / Parallel / Multi-device daisy-chain |
| Boîtier | — | 20-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Code | — | L (PLCC-20, leaded) |
| JTAG Compliance | — | IEEE 1149.1 (TAP controller with 4-wire interface) |
| DC Input Voltage (absolute max) | — | -0.3 V to +7.0 V (transients to -2.0 V / +7.0 V for <20 ns) |
| Lead-Free / RoHS | — | Lead finish version dependent (Pb-free and SnPb variants exist) |
| Programming Cycles | — | 100 typical (flash endurance, per datasheet) |