EPC2L20N vs EPC2LC02N Comparación
Comparación detallada lado a lado de EPC2L20N por Altera y EPC2LC02N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2L20N | EPC2LC02N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | Memory ICs | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,20 | $3,40 |
| Función | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs | — |
| Tamaño de memoria | 1.6 Mbit | — |
| Programmable Type | In System Programmable (ISP) | — |
| Supply Voltage - VCCINT/VCCIO | 3.0 V to 3.6 V or 4.5 V to 5.5 V | — |
| Encapsulado / Carcasa | 20-LCC (J-Lead), PLCC-20 | — |
| Packaging | Tube | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Supported FPGA Families | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) | APEX II, APEX 20K, ACEX 1K, FLEX 10K, Mercury, Stratix (partial) |
| Configuration Interface | Serial (Altera FPP / PS configuration scheme) | — |
| Cascade Support | Yes (multi-PROM chain via CE control) | — |
| Programming Method | In-system via 4-wire ISP / JTAG-style | — |
| Tipo de montaje | Surface Mount (J-Lead PLCC) | Surface Mount / Socket |
| Recuento de pines | 20 | — |
| Lead Finish | Matte Tin (Pb-free) | — |
| Nivel MSL | 3 (168 hours) | [DATA_NEEDED: MSL level] |
| Estado RoHS | Compliant | — |
| Device Type | — | Enhanced Configuration Device (Configuration PROM) |
| Memory Density | — | 1.6 Mbit |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Interfaz | — | Serial or Parallel FPGA configuration, JTAG (IEEE 1149.1) ISP |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| Configuration Mode | — | Serial / Parallel / Multi-device daisy-chain |
| Encapsulado | — | 20-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Code | — | L (PLCC-20, leaded) |
| JTAG Compliance | — | IEEE 1149.1 (TAP controller with 4-wire interface) |
| DC Input Voltage (absolute max) | — | -0.3 V to +7.0 V (transients to -2.0 V / +7.0 V for <20 ns) |
| Lead-Free / RoHS | — | Lead finish version dependent (Pb-free and SnPb variants exist) |
| Programming Cycles | — | 100 typical (flash endurance, per datasheet) |