EPC2LC22N vs EPC2LI20N Vergleich
Detaillierter Direktvergleich von EPC2LC22N von Altera und EPC2LI20N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2LC22N | EPC2LI20N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $5,10 |
| Speichertyp | Configuration PROM (non-volatile) | Non-volatile configuration PROM (Flash) |
| Speichergröße | 1.6 Mbit | 1.6 Mbit |
| Versorgungsspannung | 2.5 V (LC core) | — |
| Schnittstelle | Serial configuration / JTAG (IEEE 1149.1) | — |
| Programmability | In-system programmable (ISP) via JTAG | — |
| Cascadable | Yes - supports multi-device configuration chains | — |
| Gehäuse | PLCC-22 (Plastic Leaded Chip Carrier) | — |
| Montageart | Surface Mount / Through Hole socket | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Compatibility | Altera APEX, ACEX, Mercury, Cyclone, Stratix series FPGAs | — |
| JTAG Pins | TCK, TMS, TDI, TDO | — |
| Internal Oscillator | Yes (built-in configuration timing) | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Status | Legacy / Obsolete (replaced by flash-based FPGA configuration) | — |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| Gehäuse / Bauform | — | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |