EPC2LC22N vs EPC2LI20N Comparaison
Comparaison détaillée côte à côte de EPC2LC22N par Altera et EPC2LI20N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LC22N | EPC2LI20N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $5,10 |
| Type de mémoire | Configuration PROM (non-volatile) | Non-volatile configuration PROM (Flash) |
| Taille de mémoire | 1.6 Mbit | 1.6 Mbit |
| Tension d'alimentation | 2.5 V (LC core) | — |
| Interface | Serial configuration / JTAG (IEEE 1149.1) | — |
| Programmability | In-system programmable (ISP) via JTAG | — |
| Cascadable | Yes - supports multi-device configuration chains | — |
| Boîtier | PLCC-22 (Plastic Leaded Chip Carrier) | — |
| Type de montage | Surface Mount / Through Hole socket | Surface Mount |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Compatibility | Altera APEX, ACEX, Mercury, Cyclone, Stratix series FPGAs | — |
| JTAG Pins | TCK, TMS, TDI, TDO | — |
| Internal Oscillator | Yes (built-in configuration timing) | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Status | Legacy / Obsolete (replaced by flash-based FPGA configuration) | — |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| Boîtier / Format | — | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |