EPC448PC-20 vs EPC2LI20 Vergleich

Detaillierter Direktvergleich von EPC448PC-20 von Altera und EPC2LI20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPC448PC-20 EPC2LI20
Marke Altera Altera
Kategorie Memory ICs Memory ICs
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,25 $5,95
Device Family Enhanced Configuration Device (EPC) —
Memory Density 4 Mbit (4,194,304 bits) —
Speed Grade -20 —
Supply Voltage (VCC) 3.3 V —
Configuration Clock (Max) 20 MHz —
Interface to FPGA Dedicated Altera/Intel configuration serial (Active Serial) —
Programming Interface JTAG (IEEE 1149.1) ISP —
Gehäuse 20-ball PC-BGA —
Montageart Surface Mount Surface Mount (PLCC socket-compatible)
Betriebstemperatur [DATA_NEEDED: operating temperature range] -40 C to +85 C (Industrial)
Configuration Time (typical 4 Mbit) Approx. 200 ms at 20 MHz —
Supported FPGA Series APEX 20K, ACEX 1K, Cyclone, Cyclone II/III, Stratix/Stratix II —
Compression Supported (1.5x to 2x depending on bitstream) —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Speichergröße — 1.6 Mb (1,572,864 bits)
Speichertyp — Flash (in-system programmable)
Programmable Type — In System Programmable (ISP)
Funktion — Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating — 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
Gehäuse / Bauform — 20-PLCC (J-lead, 9x9 mm)
Configuration Interface — Serial or Byte-wide (parallel)
Decompression — On-chip (supports compressed bitstreams)
JTAG / ISP Interface — IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support — Yes (daisy-chain configuration)
User-Accessible Memory — Yes (unused flash available to user logic)
MSL-Level — [DATA_NEEDED: MSL level]

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