EPC448PC-20 vs EPC2LI20 Comparación
Comparación detallada lado a lado de EPC448PC-20 por Altera y EPC2LI20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC448PC-20 | EPC2LI20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,25 | $5,95 |
| Device Family | Enhanced Configuration Device (EPC) | — |
| Memory Density | 4 Mbit (4,194,304 bits) | — |
| Speed Grade | -20 | — |
| Supply Voltage (VCC) | 3.3 V | — |
| Configuration Clock (Max) | 20 MHz | — |
| Interface to FPGA | Dedicated Altera/Intel configuration serial (Active Serial) | — |
| Programming Interface | JTAG (IEEE 1149.1) ISP | — |
| Encapsulado | 20-ball PC-BGA | — |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket-compatible) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (Industrial) |
| Configuration Time (typical 4 Mbit) | Approx. 200 ms at 20 MHz | — |
| Supported FPGA Series | APEX 20K, ACEX 1K, Cyclone, Cyclone II/III, Stratix/Stratix II | — |
| Compression | Supported (1.5x to 2x depending on bitstream) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Tamaño de memoria | — | 1.6 Mb (1,572,864 bits) |
| Tipo de memoria | — | Flash (in-system programmable) |
| Programmable Type | — | In System Programmable (ISP) |
| Función | — | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| Encapsulado / Carcasa | — | 20-PLCC (J-lead, 9x9 mm) |
| Configuration Interface | — | Serial or Byte-wide (parallel) |
| Decompression | — | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | — | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | — | Yes (daisy-chain configuration) |
| User-Accessible Memory | — | Yes (unused flash available to user logic) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |