EPM240T100C3N vs EPM240GT100C5N Vergleich
Detaillierter Direktvergleich von EPM240T100C3N von Altera und EPM240GT100C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM240T100C3N | EPM240GT100C5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,05 | $9,20 |
| Series | MAX II | EPM240 |
| Device Family | MAX II CPLD (EPM240) | — |
| Logic Elements (LE) | 240 | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 80 | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Gehäuse | 100-pin TQFP (14x14 mm) | 100-pin TQFP (T100) |
| Configuration Memory | Internal Flash (non-volatile) | Non-volatile Flash (instant-on) |
| Pin-to-Pin Logic Delay (tPD) | 4.4 ns (typical) | — |
| Maximum Operating Frequency | 200 MHz (internal oscillator) | — |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 2.5 V or 3.3 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Betriebstemperatur | 0 °C to +85 °C (commercial) | 0C to +85C (Commercial) |
| Quiescent Current (typical) | 35 mA | — |
| RoHS-Status | Compliant | Compliant |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL rating] | 3 |
| Family | — | MAX II |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| User I/Os | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Programmable Type | — | In-System Programmable (ISP) via JTAG |