EPM3128ATC144-10 vs EPM3128ATC144-5N Vergleich
Detaillierter Direktvergleich von EPM3128ATC144-10 von Altera und EPM3128ATC144-5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera
EPM3128ATC144-5N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3128ATC144-10 | EPM3128ATC144-5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,20 | $13,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | — |
| User I/Os | 96 | — |
| Usable Gates | 2,500 (typical) | 2500 |
| Logic Elements / LABs | 4 Logic Array Blocks | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| Counter Frequency (fCNT) | Up to 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Interface | 1.5V / 1.8V / 2.5V / 3.3V | — |
| In-System Programmability | IEEE Std. 1532 compliant | Yes (3.3-V via JTAG) |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Gehäuse | 144-pin TQFP (TQ144) | 144-pin TQFP (20x20 mm) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to 70C (Commercial) |
| RoHS-Status | Compliant | Compliant (lead-free) |
| Lead-Free | Yes | — |
| Logic Family | — | CMOS |
| Macrocells | — | 128 |
| User I/O | — | 96 |
| Pin-to-Pin Logic Delay | — | 5 ns |
| Counter Frequency | — | up to 227.3 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Logic Levels Supported | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| JTAG Boundary Scan | — | IEEE Std 1149.1 compliant |