EPM3128ATC144-10 vs EPM3128ATC144-5N 对比

详细并排对比 EPM3128ATC144-10 出自 Altera 和 EPM3128ATC144-5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3128ATC144-5N EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N ⚠ 最后一次采购

规格对比

参数 EPM3128ATC144-10 EPM3128ATC144-5N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 最后采购期
库存状态 有库存 有库存
单价(USD) $6.20 $13.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macro Cells 128 —
User I/Os 96 —
Usable Gates 2,500 (typical) 2500
Logic Elements / LABs 4 Logic Array Blocks —
Propagation Delay (tPD) 10 ns (speed grade -10) —
Counter Frequency (fCNT) Up to 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
MultiVolt I/O Interface 1.5V / 1.8V / 2.5V / 3.3V —
In-System Programmability IEEE Std. 1532 compliant Yes (3.3-V via JTAG)
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) —
Configuration Memory EEPROM (non-volatile, instant-on) —
封装 144-pin TQFP (TQ144) 144-pin TQFP (20x20 mm)
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (commercial) 0C to 70C (Commercial)
RoHS 状态 Compliant Compliant (lead-free)
Lead-Free Yes —
Logic Family — CMOS
Macrocells — 128
User I/O — 96
Pin-to-Pin Logic Delay — 5 ns
Counter Frequency — up to 227.3 MHz
Supply Voltage (Core) — 3.3 V
I/O Logic Levels Supported — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
JTAG Boundary Scan — IEEE Std 1149.1 compliant

数据手册与资源

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