EPM3512AFC256-23 vs EPM3256AFC256-10N Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-23 von Altera und EPM3256AFC256-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AFC256-23 | EPM3256AFC256-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,75 | $25,95 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 256 |
| Usable Gates | 10,000 | 5,000 gates |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | — |
| Maximum Operating Frequency | 178.6 MHz | — |
| Propagation Delay (tPD) | 5.5 ns | — |
| Pin-to-Pin Delay | 23 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for FC256] | — |
| Gehäuse | 256-ball FineLine BGA (FC256), 17 mm x 17 mm | 256-pin FineLine BGA |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | 0 C to 70 C (commercial) |
| Montageart | Surface Mount (BGA) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | — | 161 |
| Pin-to-Pin Logic Delay | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Core Voltage | — | 3.3 V |
| I/O Logic Level Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) |
| Logic Family | — | CMOS |
| PCI Compliance | — | PCI Local Bus Specification Rev 2.2 (at -10 grade) |