EPM5016LC-17 vs EPM5032LC-20 Vergleich
Detaillierter Direktvergleich von EPM5016LC-17 von Altera und EPM5032LC-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5016LC-17 | EPM5032LC-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,95 | $8,40 |
| Family | MAX 5000 EPLD | — |
| Technology | CMOS, UV-erasable | — |
| Macrocells | 16 | 32 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Total Input Pins | 16 | — |
| Outputs | 8 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 17 ns | 20 ns |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | — |
| Gehäuse | Windowed Ceramic DIP (LC) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | — |
| Betriebstemperatur | [DATA_NEEDED: temperature grade] | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Logic Compatibility | TTL/CMOS | — |
| Device Family | — | MAX 5000 |
| Product Type | — | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Usable Gates | — | 600 gates |
| Logic Blocks (LABs) | — | 1 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Maximum Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Bidirectional I/O Pins | — | 16 |
| Total Inputs | — | 24 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Montageart | — | Surface Mount |
| MSL-Level | — | [DATA_NEEDED: MSL] |