EPM5032DC-25 vs EPM5032DI-25 Vergleich
Detaillierter Direktvergleich von EPM5032DC-25 von Altera und EPM5032DI-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032DC-25 | EPM5032DI-25 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,55 | $18,20 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Product Family | MAX 5000 | — |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | 32 | 32 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Counter Frequency (fCNT) | [DATA_NEEDED: maximum counter frequency] | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Number of Dedicated Inputs | 32 (in DIP-28 pinout) | — |
| Number of I/O Pins | 22 (in DIP-28 pinout, 4 used as dedicated inputs) | — |
| Gehäuse | CDIP-28 (Windowed Ceramic DIP-28) | Ceramic DIP, windowed (UV-erasable) |
| Process Technology | CMOS, EPROM (UV-Erasable) | CMOS |
| Architecture | PAL-Type, Single-LAB, 32-Macrocell | PAL-type, CMOS, AND-OR sum-of-products |
| Output Structure | Programmable I/O with output enable | — |
| Flip-Flop Configuration | D, T, JK, or SR (programmable) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS-Status | Lead Free / RoHS Compliant (per distributor listings) | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Programming Method | UV erase + Altera/Intel MAX+PLUS II programmer | — |
| Erasure Method | UV light through ceramic window | — |
| Family | — | MAX 5000 |
| Product Terms | — | 320 |
| Logic Gates | — | [DATA_NEEDED: equivalent gate count] |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Total Array Inputs | — | 24 |
| Registered Outputs | — | 16 |
| Global Clocks | — | 1 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Versorgungsspannung | — | 5 V |
| Pin-Anzahl | — | [DATA_NEEDED: exact pin count - 24 or 28] |
| I/O Standard | — | TTL-compatible |
| Programmability | — | UV-erasable, EPROM-based |
| Development Tool | — | MAX+PLUS II / A+PLUS |
| Lifecycle | — | Not Recommended for New Designs (NRND) |