EPM5032DC-25 vs EPM5032DI-25 对比

详细并排对比 EPM5032DC-25 出自 Altera 和 EPM5032DI-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5032DC-25 EPM5032DI-25
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $3.55 $18.20
Manufacturer Altera (Intel Programmable Solutions Group) —
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (EPLD) UV-erasable Programmable Logic Device (PLD)
Macrocells 32 32
Pin-to-Pin Propagation Delay (tPD) 25 ns —
Maximum Counter Frequency (fCNT) [DATA_NEEDED: maximum counter frequency] —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Number of Dedicated Inputs 32 (in DIP-28 pinout) —
Number of I/O Pins 22 (in DIP-28 pinout, 4 used as dedicated inputs) —
封装 CDIP-28 (Windowed Ceramic DIP-28) Ceramic DIP, windowed (UV-erasable)
Process Technology CMOS, EPROM (UV-Erasable) CMOS
Architecture PAL-Type, Single-LAB, 32-Macrocell PAL-type, CMOS, AND-OR sum-of-products
Output Structure Programmable I/O with output enable —
Flip-Flop Configuration D, T, JK, or SR (programmable) —
工作温度 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
RoHS 状态 Lead Free / RoHS Compliant (per distributor listings) [DATA_NEEDED: likely non-compliant due to ceramic DIP]
Programming Method UV erase + Altera/Intel MAX+PLUS II programmer —
Erasure Method UV light through ceramic window —
Family — MAX 5000
Product Terms — 320
Logic Gates — [DATA_NEEDED: equivalent gate count]
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Registered Outputs — 16
Global Clocks — 1
Propagation Delay (tPD) — 25 ns
Maximum Clock Frequency (fMAX) — 62.5 MHz
电源电压 — 5 V
引脚数量 — [DATA_NEEDED: exact pin count - 24 or 28]
I/O Standard — TTL-compatible
Programmability — UV-erasable, EPROM-based
Development Tool — MAX+PLUS II / A+PLUS
Lifecycle — Not Recommended for New Designs (NRND)

数据手册与资源

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