EPM5032DC-25 vs EPM5032DI-25 比較

詳細な並列比較: EPM5032DC-25 メーカー: Altera および EPM5032DI-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5032DC-25 EPM5032DI-25
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 NRND NRND
在庫状況 In Stock In Stock
単価(USD) $3.55 $18.20
Manufacturer Altera (Intel Programmable Solutions Group) —
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (EPLD) UV-erasable Programmable Logic Device (PLD)
Macrocells 32 32
Pin-to-Pin Propagation Delay (tPD) 25 ns —
Maximum Counter Frequency (fCNT) [DATA_NEEDED: maximum counter frequency] —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Number of Dedicated Inputs 32 (in DIP-28 pinout) —
Number of I/O Pins 22 (in DIP-28 pinout, 4 used as dedicated inputs) —
パッケージ CDIP-28 (Windowed Ceramic DIP-28) Ceramic DIP, windowed (UV-erasable)
Process Technology CMOS, EPROM (UV-Erasable) CMOS
Architecture PAL-Type, Single-LAB, 32-Macrocell PAL-type, CMOS, AND-OR sum-of-products
Output Structure Programmable I/O with output enable —
Flip-Flop Configuration D, T, JK, or SR (programmable) —
動作温度 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
RoHS ステータス Lead Free / RoHS Compliant (per distributor listings) [DATA_NEEDED: likely non-compliant due to ceramic DIP]
Programming Method UV erase + Altera/Intel MAX+PLUS II programmer —
Erasure Method UV light through ceramic window —
Family — MAX 5000
Product Terms — 320
Logic Gates — [DATA_NEEDED: equivalent gate count]
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Registered Outputs — 16
Global Clocks — 1
Propagation Delay (tPD) — 25 ns
Maximum Clock Frequency (fMAX) — 62.5 MHz
電源電圧 — 5 V
ピン数 — [DATA_NEEDED: exact pin count - 24 or 28]
I/O Standard — TTL-compatible
Programmability — UV-erasable, EPROM-based
Development Tool — MAX+PLUS II / A+PLUS
Lifecycle — Not Recommended for New Designs (NRND)

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