EPM5032DC vs EPM5032JC Vergleich
Detaillierter Direktvergleich von EPM5032DC von Altera und EPM5032JC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032DC | EPM5032JC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,40 | $13,50 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Gehäuse | DIP-24 (ceramic, windowed) | PLCC-44 |
| Speed Grade | DC (commercial) | — |
| Betriebstemperatur | 0C to +70C | 0C to +70C (commercial) |
| Technology | Bipolar EPROM, UV-erasable | — |
| Programmable Logic Elements | AND array + fixed OR array per macrocell | — |
| Configuration Memory | EPROM (UV-erasable via package window) | — |
| Montageart | Through-hole (DIP) | Surface Mount (J-lead) |
| Pin-Anzahl | 24 | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Programming Tool | Altera MAX+PLUS II / A+PLUS legacy | — |
| Lebenszyklusstatus | Obsolete (mature legacy) | — |
| Logic Gates | — | 600 usable gates |
| Maximum I/O Pins | — | 40 |
| Propagation Delay (tPD) | — | [DATA_NEEDED: specific speed grade value] |
| Supply Voltage (VCC) | — | 5 V |
| Input Type | — | TTL-compatible |
| Ausgangstyp | — | TTL/CMOS-compatible |
| Programmability | — | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | — | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | — | JEDEC PLCC-44 footprint |
| Lead-Free | — | unknown |