EPM5032DC vs EPM5032JC 对比
详细并排对比 EPM5032DC 出自 Altera 和 EPM5032JC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5032DC | EPM5032JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.40 | $13.50 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| 封装 | DIP-24 (ceramic, windowed) | PLCC-44 |
| Speed Grade | DC (commercial) | — |
| 工作温度 | 0C to +70C | 0C to +70C (commercial) |
| Technology | Bipolar EPROM, UV-erasable | — |
| Programmable Logic Elements | AND array + fixed OR array per macrocell | — |
| Configuration Memory | EPROM (UV-erasable via package window) | — |
| 安装类型 | Through-hole (DIP) | Surface Mount (J-lead) |
| 引脚数量 | 24 | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | unknown |
| Programming Tool | Altera MAX+PLUS II / A+PLUS legacy | — |
| 生命周期状态 | Obsolete (mature legacy) | — |
| Logic Gates | — | 600 usable gates |
| Maximum I/O Pins | — | 40 |
| Propagation Delay (tPD) | — | [DATA_NEEDED: specific speed grade value] |
| Supply Voltage (VCC) | — | 5 V |
| Input Type | — | TTL-compatible |
| 输出类型 | — | TTL/CMOS-compatible |
| Programmability | — | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | — | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | — | JEDEC PLCC-44 footprint |
| Lead-Free | — | unknown |