EPM5032LC-20 vs EPM5032LC-25 Vergleich
Detaillierter Direktvergleich von EPM5032LC-20 von Altera und EPM5032LC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032LC-20 | EPM5032LC-25 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,40 | $8,20 |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | EPLD / CPLD (One-Time Programmable / UV-Erasable) | — |
| Usable Gates | 600 gates | — |
| Macrocells | 32 | 32 |
| Logic Blocks (LABs) | 1 | — |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Maximum Frequency | 71.4 MHz | — |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| Supply Voltage (VCC) | 5 V ±5% | 5 V ±10% (4.5 V to 5.5 V) |
| Betriebstemperatur | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) | 0 °C to +70 °C (commercial, "LC" suffix) |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs | 24 | 24 (7 dedicated + 16 I/O used as input) |
| Output Functions | 16 | — |
| Product Terms per Output | 16 | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Gehäuse | LCC-28 (Plastic Leaded Chip Carrier, J-lead) | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch |
| Montageart | Surface Mount | Surface Mount, socket-compatible |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Not RoHS compliant (legacy Altera product) |
| MSL-Level | [DATA_NEEDED: MSL] | — |
| Architecture | — | PAL-type EPLD (Erasable Programmable Logic Device) |
| Technology | — | CMOS, UV-erasable / OTP |
| Product Terms | — | 320 |
| I/O Pins | — | 16 bidirectional |
| Maximum Internal Frequency | — | 62.5 MHz |
| I/O Standard | — | 5 V CMOS |
| Configuration Cell | — | Programmable interconnect array (PIA), OTP / UV-erasable |