EPM5032LC-20 vs EPM5032LC-25 比較
詳細な並列比較: EPM5032LC-20 メーカー: Altera および EPM5032LC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032LC-20 | EPM5032LC-25 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.40 | $8.20 |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | EPLD / CPLD (One-Time Programmable / UV-Erasable) | — |
| Usable Gates | 600 gates | — |
| Macrocells | 32 | 32 |
| Logic Blocks (LABs) | 1 | — |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Maximum Frequency | 71.4 MHz | — |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| Supply Voltage (VCC) | 5 V ±5% | 5 V ±10% (4.5 V to 5.5 V) |
| 動作温度 | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) | 0 °C to +70 °C (commercial, "LC" suffix) |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs | 24 | 24 (7 dedicated + 16 I/O used as input) |
| Output Functions | 16 | — |
| Product Terms per Output | 16 | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| パッケージ | LCC-28 (Plastic Leaded Chip Carrier, J-lead) | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch |
| 実装タイプ | Surface Mount | Surface Mount, socket-compatible |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Not RoHS compliant (legacy Altera product) |
| MSLレベル | [DATA_NEEDED: MSL] | — |
| Architecture | — | PAL-type EPLD (Erasable Programmable Logic Device) |
| Technology | — | CMOS, UV-erasable / OTP |
| Product Terms | — | 320 |
| I/O Pins | — | 16 bidirectional |
| Maximum Internal Frequency | — | 62.5 MHz |
| I/O Standard | — | 5 V CMOS |
| Configuration Cell | — | Programmable interconnect array (PIA), OTP / UV-erasable |