EPM5032LC-20 vs EPM5032PC-20 Vergleich

Detaillierter Direktvergleich von EPM5032LC-20 von Altera und EPM5032PC-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5032LC-20 EPM5032PC-20
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $8,40 $7,05
Device Family MAX 5000 MAX 5000
Product Type EPLD / CPLD (One-Time Programmable / UV-Erasable) —
Usable Gates 600 gates 600
Macrocells 32 32
Logic Blocks (LABs) 1 —
Speed Grade -20 (20 ns pin-to-pin) —
Maximum Frequency 71.4 MHz —
Propagation Delay (tPD) 20 ns 20 ns
Supply Voltage (VCC) 5 V ±5% 4.75 V to 5.25 V (nominal 5 V)
Betriebstemperatur 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) [DATA_NEEDED: operating temperature range]
Dedicated Inputs 7 24
Bidirectional I/O Pins 16 —
Total Inputs 24 —
Output Functions 16 —
Product Terms per Output 16 —
Programmable Interconnect Programmable Interconnect Array (PIA) —
Gehäuse LCC-28 (Plastic Leaded Chip Carrier, J-lead) PDIP-28 (Plastic DIP, 28-pin)
Montageart Surface Mount Through-Hole
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
MSL-Level [DATA_NEEDED: MSL] —
Device Type — CPLD (Complex Programmable Logic Device)
Programming Type — OTP (One-Time Programmable)
Logic Blocks — 2 Logic Array Blocks
Product Terms — 320
Bidirectional I/O Lines — 16
Maximale Taktfrequenz — 62.5 MHz
Technology — CMOS, 0.65 um process
Architecture — PAL-type macrocells with Programmable Interconnect Array (PIA)

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