EPM5064JC vs EPM5064JC-2 Vergleich
Detaillierter Direktvergleich von EPM5064JC von Altera und EPM5064JC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5064JC | EPM5064JC-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $23,10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | — |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | 1250 |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| Gehäuse | 68-pin PLCC (JEDEC) | 28-pin CLCC (J-lead, ceramic, windowed) |
| Montageart | Surface Mount (socketed) | — |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 5 V (4.75 V to 5.25 V) |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: commercial or industrial grade] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 45 ns |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 28 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV-erase + EPROM programmer (not ISP) |
| Compliance | — | RoHS status unknown (ceramic/J-lead windowed part, legacy product) |