EPM5064JC vs EPM5064JC-2 Comparison
Detailed side-by-side comparison of EPM5064JC by Altera and EPM5064JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064JC | EPM5064JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $23.10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | β |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | 1250 |
| Logic Array Inputs | 36 | β |
| Logic Array Outputs | 64 | β |
| Package | 68-pin PLCC (JEDEC) | 28-pin CLCC (J-lead, ceramic, windowed) |
| Mounting Type | Surface Mount (socketed) | β |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 5 V (4.75 V to 5.25 V) |
| I/O Logic Level | TTL / CMOS compatible | β |
| Configuration Memory | EPROM (UV-erasable window or OTP) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: commercial or industrial grade] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | β |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | β |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | β |
| Logic Array Blocks (LABs) | β | 4 |
| Propagation Delay (tPD) | β | 45 ns |
| Maximum Clock Frequency (fMAX) | β | 50 MHz |
| Dedicated Inputs | β | 7 |
| I/O Pins | β | 28 |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Technology | β | CMOS, UV-erasable EPROM |
| Programming Method | β | UV-erase + EPROM programmer (not ISP) |
| Compliance | β | RoHS status unknown (ceramic/J-lead windowed part, legacy product) |