EPM5064JC vs EPM5064JC-2 比較
詳細な並列比較: EPM5064JC メーカー: Altera および EPM5064JC-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064JC | EPM5064JC-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.10 | $23.10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | — |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | 1250 |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| パッケージ | 68-pin PLCC (JEDEC) | 28-pin CLCC (J-lead, ceramic, windowed) |
| 実装タイプ | Surface Mount (socketed) | — |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 5 V (4.75 V to 5.25 V) |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| 動作温度 | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: commercial or industrial grade] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 45 ns |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 28 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV-erase + EPROM programmer (not ISP) |
| Compliance | — | RoHS status unknown (ceramic/J-lead windowed part, legacy product) |