EPM5064JC vs EPM5064JI-1 Vergleich

Detaillierter Direktvergleich von EPM5064JC von Altera und EPM5064JI-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5064JC EPM5064JI-1
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $7,10 $3,40
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) EPLD (Erasable Programmable Logic Device)
Macrocells 64 64
Usable Gates 1,250 (approx.) —
Logic Array Inputs 36 —
Logic Array Outputs 64 —
Gehäuse 68-pin PLCC (JEDEC) 68-pin PLCC (windowed ceramic)
Montageart Surface Mount (socketed) Surface Mount
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) —
I/O Logic Level TTL / CMOS compatible —
Configuration Memory EPROM (UV-erasable window or OTP) —
Betriebstemperatur [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: commercial vs industrial grade temp range]
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] —
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: not stated in provided data]
Lead-Free [DATA_NEEDED: lead-free status] —
MSL-Level [DATA_NEEDED: MSL rating] —
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) —
User I/O Pins — [DATA_NEEDED: user I/O count from datasheet]
Logic Elements — [DATA_NEEDED: total logic elements]
Propagation Delay (tPD) — [DATA_NEEDED: combinational tPD from datasheet]
Versorgungsspannung — 5 V
Process Technology — CMOS, UV-erasable
Speed Grade — JI-1 (commercial, -10/-12/-15 family)
Programmability — UV-erasable (windowed package)
Data Retention — 25 years (per MAX 5000 datasheet)

Datenblätter & Ressourcen

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