EPM5064JC vs EPM5064LI Vergleich

Detaillierter Direktvergleich von EPM5064JC von Altera und EPM5064LI von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5064JC EPM5064LI
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $7,10 $9,95
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Usable Gates 1,250 (approx.) —
Logic Array Inputs 36 —
Logic Array Outputs 64 —
Gehäuse 68-pin PLCC (JEDEC) —
Montageart Surface Mount (socketed) Surface Mount
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) 4.5 V to 5.5 V
I/O Logic Level TTL / CMOS compatible —
Configuration Memory EPROM (UV-erasable window or OTP) UV-Erasable / OTP (EPROM-based)
Betriebstemperatur [DATA_NEEDED: operating temperature grade] —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] —
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: confirm RoHS status - legacy Altera part]
Lead-Free [DATA_NEEDED: lead-free status] —
MSL-Level [DATA_NEEDED: MSL rating] —
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) —
Logic Array Blocks (LABs) — 4
Number of Terminals — 44
Package Code — QCCJ (PLCC-44, J-bend)
Package Shape — Square
Operating Temperature Grade — Industrial
Maximale Taktfrequenz — 33.3 MHz
Propagation Delay (tPD) — 55 ns (typical)
I/O Pins — 28 bidirectional
Dedicated Inputs — 7
Total User Inputs — 36
Process Technology — 1-micron EPIC CMOS
Latch-up Immunity — 500 mA typical at 125 C

Datenblätter & Ressourcen

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