EPM5064JC vs EPM5064LI 比較
詳細な並列比較: EPM5064JC メーカー: Altera および EPM5064LI メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064JC | EPM5064LI |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.10 | $9.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | — |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| パッケージ | 68-pin PLCC (JEDEC) | — |
| 実装タイプ | Surface Mount (socketed) | Surface Mount |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 4.5 V to 5.5 V |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | UV-Erasable / OTP (EPROM-based) |
| 動作温度 | [DATA_NEEDED: operating temperature grade] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: confirm RoHS status - legacy Altera part] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Logic Array Blocks (LABs) | — | 4 |
| Number of Terminals | — | 44 |
| Package Code | — | QCCJ (PLCC-44, J-bend) |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Industrial |
| 最大クロック周波数 | — | 33.3 MHz |
| Propagation Delay (tPD) | — | 55 ns (typical) |
| I/O Pins | — | 28 bidirectional |
| Dedicated Inputs | — | 7 |
| Total User Inputs | — | 36 |
| Process Technology | — | 1-micron EPIC CMOS |
| Latch-up Immunity | — | 500 mA typical at 125 C |