EPM5064JC vs EPM5064LI 비교
다음의 상세 나란히 비교: EPM5064JC 제조: Altera 및 EPM5064LI 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5064JC | EPM5064LI |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $7.10 | $9.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | — |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| 패키지 | 68-pin PLCC (JEDEC) | — |
| 실장 유형 | Surface Mount (socketed) | Surface Mount |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 4.5 V to 5.5 V |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | UV-Erasable / OTP (EPROM-based) |
| 동작 온도 | [DATA_NEEDED: operating temperature grade] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: confirm RoHS status - legacy Altera part] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Logic Array Blocks (LABs) | — | 4 |
| Number of Terminals | — | 44 |
| Package Code | — | QCCJ (PLCC-44, J-bend) |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Industrial |
| 최대 클록 주파수 | — | 33.3 MHz |
| Propagation Delay (tPD) | — | 55 ns (typical) |
| I/O Pins | — | 28 bidirectional |
| Dedicated Inputs | — | 7 |
| Total User Inputs | — | 36 |
| Process Technology | — | 1-micron EPIC CMOS |
| Latch-up Immunity | — | 500 mA typical at 125 C |