EPM5064LC-1 vs EPM5064JC Vergleich

Detaillierter Direktvergleich von EPM5064LC-1 von Altera und EPM5064JC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5064LC-1 EPM5064JC
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $7,10
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 MAX 5000
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
Usable Gates 1.25K (approx.) 1,250 (approx.)
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V (typical, 4.75 V - 5.25 V range)
Internal Operating Frequency 62.5 MHz —
Propagation Delay (tPD) 40 ns —
Input Lines 36 —
Dedicated Inputs 7 —
Output Lines 28 —
Programming Technology OTP / UV-Erasable EPROM —
Gehäuse 44-pin PLCC (Plastic Leaded Chip Carrier) 68-pin PLCC (JEDEC)
Process Technology CMOS —
Betriebstemperatur [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature grade]
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Programming Interface JTAG (ByteBlaster-compatible) —
Device Type — EPLD (Erasable PLD)
Logic Array Inputs — 36
Logic Array Outputs — 64
Montageart — Surface Mount (socketed)
I/O Logic Level — TTL / CMOS compatible
Configuration Memory — EPROM (UV-erasable window or OTP)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL-Level — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

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