EPM5064LC-1 vs EPM5064JC 比較
詳細な並列比較: EPM5064LC-1 メーカー: Altera および EPM5064JC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064LC-1 | EPM5064JC |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $7.10 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1.25K (approx.) | 1,250 (approx.) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (typical, 4.75 V - 5.25 V range) |
| Internal Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | — |
| Input Lines | 36 | — |
| Dedicated Inputs | 7 | — |
| Output Lines | 28 | — |
| Programming Technology | OTP / UV-Erasable EPROM | — |
| パッケージ | 44-pin PLCC (Plastic Leaded Chip Carrier) | 68-pin PLCC (JEDEC) |
| Process Technology | CMOS | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Programming Interface | JTAG (ByteBlaster-compatible) | — |
| Device Type | — | EPLD (Erasable PLD) |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| 実装タイプ | — | Surface Mount (socketed) |
| I/O Logic Level | — | TTL / CMOS compatible |
| Configuration Memory | — | EPROM (UV-erasable window or OTP) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSLレベル | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |