EPM5064LC-2 vs EPM5064LI Vergleich

Detaillierter Direktvergleich von EPM5064LC-2 von Altera und EPM5064LI von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5064LC-2 EPM5064LI
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $8,40 $9,95
Device Family MAX 5000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 64
Logic Array Blocks (LABs) 4 4
Logic Elements per LAB 16 —
Number of Inputs 36 (7 dedicated + 28 I/O) —
Number of I/O Pins 28 —
Number of Flip-Flops 28 —
Propagation Delay (tPD) 45 ns 55 ns (typical)
Maximum Internal Frequency 40 MHz —
Process Technology CMOS, OTP EPROM (UV-erasable base) 1-micron EPIC CMOS
Programmable Polarity Yes —
Programmable Output Enable Yes, per macrocell —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.5 V to 5.5 V
Betriebstemperatur -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] —
Gehäuse PLCC-44 (J-Lead, plastic) —
Montageart Surface Mount Surface Mount
RoHS-Status [DATA_NEEDED: not specified in source] [DATA_NEEDED: confirm RoHS status - legacy Altera part]
Programming Method Altera byte-wide / JTAG programmer —
Family — MAX 5000
Device Type — CPLD (Complex Programmable Logic Device)
Number of Terminals — 44
Package Code — QCCJ (PLCC-44, J-bend)
Package Shape — Square
Configuration Memory — UV-Erasable / OTP (EPROM-based)
Operating Temperature Grade — Industrial
Maximale Taktfrequenz — 33.3 MHz
I/O Pins — 28 bidirectional
Dedicated Inputs — 7
Total User Inputs — 36
Latch-up Immunity — 500 mA typical at 125 C

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