EPM5064LC-2 vs EPM5064LI 比較
詳細な並列比較: EPM5064LC-2 メーカー: Altera および EPM5064LI メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064LC-2 | EPM5064LI |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.40 | $9.95 |
| Device Family | MAX 5000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Logic Elements per LAB | 16 | — |
| Number of Inputs | 36 (7 dedicated + 28 I/O) | — |
| Number of I/O Pins | 28 | — |
| Number of Flip-Flops | 28 | — |
| Propagation Delay (tPD) | 45 ns | 55 ns (typical) |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) | 1-micron EPIC CMOS |
| Programmable Polarity | Yes | — |
| Programmable Output Enable | Yes, per macrocell | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.5 V to 5.5 V |
| 動作温度 | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] | — |
| パッケージ | PLCC-44 (J-Lead, plastic) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: not specified in source] | [DATA_NEEDED: confirm RoHS status - legacy Altera part] |
| Programming Method | Altera byte-wide / JTAG programmer | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Number of Terminals | — | 44 |
| Package Code | — | QCCJ (PLCC-44, J-bend) |
| Package Shape | — | Square |
| Configuration Memory | — | UV-Erasable / OTP (EPROM-based) |
| Operating Temperature Grade | — | Industrial |
| 最大クロック周波数 | — | 33.3 MHz |
| I/O Pins | — | 28 bidirectional |
| Dedicated Inputs | — | 7 |
| Total User Inputs | — | 36 |
| Latch-up Immunity | — | 500 mA typical at 125 C |