EPM5128JC-1 vs EPM5128GC-1 Vergleich

Detaillierter Direktvergleich von EPM5128JC-1 von Altera und EPM5128GC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5128JC-1 EPM5128GC-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $24,95 $18,95
Family MAX 5000 MAX 5000
Device Type Erasable Programmable Logic Device (EPLD/CPLD) UV-erasable CMOS CPLD
Macrocells 128 128
Usable Gates 2,500 2,500
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Maximum Operating Frequency 62.5 MHz 62.5 MHz
Pin-to-Pin Propagation Delay (tPD) 40 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM
Gehäuse 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) PGA-96+ (Pin Grid Array, ceramic windowed)
Montageart Surface Mount —
Betriebstemperatur [DATA_NEEDED: temperature grade] -40C to +85C (industrial)
Programming Interface JTAG / Altera dedicated programmer —
Configuration Memory Non-volatile EPROM (UV-erasable) —
RoHS-Status non_compliant (ceramic windowed package) [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Lebenszyklusstatus Obsolete - last-time-buy inventory only —
Dedicated Inputs — 7
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Propagation Delay (tPD) — 16 ns (typical, -1 speed grade)
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
Programming Method — UV erase + EPROM program (or device programmer)
MSL-Level — [DATA_NEEDED: MSL level]

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern