EPM5128JC-1 vs EPM5128GC-1 对比

详细并排对比 EPM5128JC-1 出自 Altera 和 EPM5128GC-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5128JC-1 EPM5128GC-1
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $24.95 $18.95
Family MAX 5000 MAX 5000
Device Type Erasable Programmable Logic Device (EPLD/CPLD) UV-erasable CMOS CPLD
Macrocells 128 128
Usable Gates 2,500 2,500
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Maximum Operating Frequency 62.5 MHz 62.5 MHz
Pin-to-Pin Propagation Delay (tPD) 40 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM
封装 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) PGA-96+ (Pin Grid Array, ceramic windowed)
安装类型 Surface Mount —
工作温度 [DATA_NEEDED: temperature grade] -40C to +85C (industrial)
Programming Interface JTAG / Altera dedicated programmer —
Configuration Memory Non-volatile EPROM (UV-erasable) —
RoHS 状态 non_compliant (ceramic windowed package) [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
生命周期状态 Obsolete - last-time-buy inventory only —
Dedicated Inputs — 7
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Propagation Delay (tPD) — 16 ns (typical, -1 speed grade)
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
Programming Method — UV erase + EPROM program (or device programmer)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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