EPM5130WC-1AA vs EPM5130WC-2 Vergleich

Detaillierter Direktvergleich von EPM5130WC-1AA von Altera und EPM5130WC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5130WC-1AA EPM5130WC-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $54,25 $62,00
Device Family MAX 5000 MAX 5000
Macrocell Count 128 128
Number of Logic Array Blocks 8 (typical for MAX 5130) —
Propagation Delay (tPD, max) 40 ns —
Maximum Toggle Frequency (fCNT) 50 MHz —
Maximum Clock Frequency (fMAX) [DATA_NEEDED: fMAX exact value] —
Dedicated Inputs 19 19
I/O Pins 48 —
Total Inputs (incl. I/O feedback) 68 —
Total Outputs 48 —
Process Technology 5 V CMOS, UV-erasable CMOS
Gehäuse Windowed Ceramic WQFP (AA suffix) —
Betriebstemperatur [DATA_NEEDED: commercial or industrial temp grade] 0 °C to 70 °C (Commercial)
Supply Voltage (VCC) 5 V nominal 4.75 V to 5.25 V
Programming Method UV erase + EPROM programming —
RoHS-Status unknown (legacy package, likely non-compliant) [DATA_NEEDED: RoHS status]
Logic-to-Pin Ratio Highest in-class per Altera marketing literature —
Product Type — UV-Erasable PLD (CPLD)
Propagation Delay (tPD) — 45 ns
User I/O Lines — 48
Total Inputs (I/O + dedicated) — 68
Package Type — 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing
Terminal Pitch — 0.650 mm
Montageart — Surface Mount
Configuration Memory — UV-erasable CMOS EEPROM cells
Speed Grade — -2 (45 ns)
Lead-Free — [DATA_NEEDED: lead-free status]
Logic Elements — AND/OR array with programmable macrocell register

Datenblätter & Ressourcen

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