EPM5192AGC84-15 vs EPM5192AGC84-20 Vergleich
Detaillierter Direktvergleich von EPM5192AGC84-15 von Altera und EPM5192AGC84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AGC84-15 | EPM5192AGC84-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $42,00 | $41,20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable/OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Internal Clock Frequency | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Process Technology | CMOS | CMOS |
| Programmable Element | UV-Erasable EPROM cell | — |
| Gehäuse | 84-pin Ceramic PGA (Pin Grid Array) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Montageart | Through-Hole | Through-Hole (Pin Grid Array socket) |
| Betriebstemperatur | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] | — |
| RoHS-Status | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Operating Temperature Grade | — | Commercial |
| Versorgungsspannung | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |