EPM5192AGC84-15 vs EPM5192AGC84-20 Comparaison
Comparaison détaillée côte à côte de EPM5192AGC84-15 par Altera et EPM5192AGC84-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AGC84-15 | EPM5192AGC84-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $42,00 | $41,20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable/OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Internal Clock Frequency | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Process Technology | CMOS | CMOS |
| Programmable Element | UV-Erasable EPROM cell | — |
| Boîtier | 84-pin Ceramic PGA (Pin Grid Array) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Type de montage | Through-Hole | Through-Hole (Pin Grid Array socket) |
| Température de fonctionnement | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] | — |
| Statut RoHS | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Operating Temperature Grade | — | Commercial |
| Tension d'alimentation | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |