EPM5192AGC84-20 vs EPM5192AJC84-15 Vergleich

Detaillierter Direktvergleich von EPM5192AGC84-20 von Altera und EPM5192AJC84-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192AGC84-20 EPM5192AJC84-15
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $41,20 $18,95
Product Type Complex Programmable Logic Device (CPLD) —
Family MAX 5000 MAX 5000
Macrocells 192 192
User I/O Pins 64 —
Dedicated Inputs 7 —
Logic Gates (typical) [DATA_NEEDED: typical gate count] —
Maximum Clock Frequency (fMAX) 66.7 MHz 83.3 MHz
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Gehäuse 84-pin Ceramic Pin Grid Array (CPGA, WPGA) 84-pin PLCC (J84C) windowed ceramic
Package Code WPGA —
Erasure Method UV-Erasable (with OTP window) —
Process Technology CMOS CMOS EPROM
Operating Temperature Grade Commercial —
Versorgungsspannung [DATA_NEEDED: VCC range] —
I/O Standard 5V CMOS / TTL compatible —
RoHS-Status [DATA_NEEDED: RoHS compliance] Non-compliant (contains Pb, ceramic windowed package)
Montageart Through-Hole (Pin Grid Array socket) Surface Mount
Device Type — EPLD (Erasable Programmable Logic Device)
Propagation Delay (tpd) — 15 ns
Supply Voltage (VCC) — 5 V (single supply)
Technology — CMOS, UV-erasable EPROM
Betriebstemperatur — [DATA_NEEDED: commercial/industrial/military grade]
Programming Method — UV-erase + EPROM programming (windowed package)
Logic Blocks — 16 Logic Array Blocks (LABs)
I/O Pins — [DATA_NEEDED: user I/O count]

Datenblätter & Ressourcen

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