EPM5192AGC84-20 vs EPM5192AJC84-15 对比

详细并排对比 EPM5192AGC84-20 出自 Altera 和 EPM5192AJC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AGC84-20 EPM5192AJC84-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $41.20 $18.95
Product Type Complex Programmable Logic Device (CPLD) —
Family MAX 5000 MAX 5000
Macrocells 192 192
User I/O Pins 64 —
Dedicated Inputs 7 —
Logic Gates (typical) [DATA_NEEDED: typical gate count] —
Maximum Clock Frequency (fMAX) 66.7 MHz 83.3 MHz
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
封装 84-pin Ceramic Pin Grid Array (CPGA, WPGA) 84-pin PLCC (J84C) windowed ceramic
Package Code WPGA —
Erasure Method UV-Erasable (with OTP window) —
Process Technology CMOS CMOS EPROM
Operating Temperature Grade Commercial —
电源电压 [DATA_NEEDED: VCC range] —
I/O Standard 5V CMOS / TTL compatible —
RoHS 状态 [DATA_NEEDED: RoHS compliance] Non-compliant (contains Pb, ceramic windowed package)
安装类型 Through-Hole (Pin Grid Array socket) Surface Mount
Device Type — EPLD (Erasable Programmable Logic Device)
Propagation Delay (tpd) — 15 ns
Supply Voltage (VCC) — 5 V (single supply)
Technology — CMOS, UV-erasable EPROM
工作温度 — [DATA_NEEDED: commercial/industrial/military grade]
Programming Method — UV-erase + EPROM programming (windowed package)
Logic Blocks — 16 Logic Array Blocks (LABs)
I/O Pins — [DATA_NEEDED: user I/O count]

数据手册与资源

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