EPM5192AGC84-20 vs EPM5192AJC84-15 Comparaison
Comparaison détaillée côte à côte de EPM5192AGC84-20 par Altera et EPM5192AJC84-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoleteComparaison des spécifications
| Paramètre | EPM5192AGC84-20 | EPM5192AJC84-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $41,20 | $18,95 |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| Boîtier | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | 84-pin PLCC (J84C) windowed ceramic |
| Package Code | WPGA | — |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | CMOS EPROM |
| Operating Temperature Grade | Commercial | — |
| Tension d'alimentation | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (contains Pb, ceramic windowed package) |
| Type de montage | Through-Hole (Pin Grid Array socket) | Surface Mount |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tpd) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Technology | — | CMOS, UV-erasable EPROM |
| Température de fonctionnement | — | [DATA_NEEDED: commercial/industrial/military grade] |
| Programming Method | — | UV-erase + EPROM programming (windowed package) |
| Logic Blocks | — | 16 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: user I/O count] |