EPM5192AJC-25 vs EPM5192AGC84-20 Vergleich
Detaillierter Direktvergleich von EPM5192AJC-25 von Altera und EPM5192AGC84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AJC-25 | EPM5192AGC84-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,20 | $41,20 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Manufacturer | Altera (now Intel PSG) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 25 ns | — |
| Gehäuse | PLCC-68 (windowed ceramic, AJC) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Pin-Anzahl | 68 | — |
| Montageart | Surface Mount | Through-Hole (Pin Grid Array socket) |
| Versorgungsspannung | 5 V (typical) | [DATA_NEEDED: VCC range] |
| Logic Blocks | MAX 5000 LABs (Logic Array Blocks) | — |
| Programmable Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Betriebstemperatur | [DATA_NEEDED: exact operating temperature range] | — |
| Erasure Method | UV-erasable (windowed ceramic package) | UV-Erasable (with OTP window) |
| Programming Technology | EPROM (non-volatile) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Military Grade | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Process Technology | — | CMOS |
| Operating Temperature Grade | — | Commercial |
| I/O Standard | — | 5V CMOS / TTL compatible |